FPGA Implementation of High Speed, Low Power architecture for Image Compression using DCT/IDCT
Image compression is an important topic in digital world. It is the art of representing the information in a compact form. We present a new design of low-power and high speed Discrete Cosine Transform (DCT) for image compression to be implemented on Field Programmable Gate Arrays (FPGAs).The architecture of DCT is based on Lo-effler method which is a fast and low complexity algorithm. The DCT optimization is based on the hardware simplification of the multipliers used to compute the DCT coefficients. Low power approaches like Canonic signed digit representation for constant coefficients and sub-expression elimination methods have been used. The 2D DCT is performed on 8x8 image matrix using two 1D DCT blocks and a transposition block. Similar to DCT, the IDCT is also implemented using the Lo-effler algorithm for IDCT. Verilog HDL is used to implement the design. ISIM of XILINX is used for the simulation of the design. X power analyzer tool of xilinx is used to obtain the detailed dynamic power report of the design. MATLAB is used as the support tool to obtain the input pixel values of the image.
Author Name: Winston A. Noronha and Vikas R. Balikai