Timing Error Tolerance in Small Core Designs for SOC Applications
In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new flip-flop design. The proposed design methods as provides timing error tolerance at the small cost of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area need are compared to previous design methods in the open literature. To validate its efficiency, it has been applied in the designs based on done. The proposed error detection and correction scheme is based on the bit-flipping flip-flop method. This is synopsized as follows: in case of error detection at the output of a flip-flop the corresponding logic value is asynchronously complemented for error correction.