Abstract

Many high-speed analog to digital converters, such as flash ADCs, require high-speed, low power comparators with small chip area. CMOS dynamic comparator with dual input, dual output inverter stage is suitable for high speed analog-to-digital converters with low voltage and low power. A single tail comparator is replaced with a double tail dynamic comparator which reduces the power and voltage by increasing the speed. The proposed Dynamic comparator is a modified version of a low voltage low power double tail comparator for area efficient and double edge triggered operation. The simulated data presented is obtained using TANNER EDA tool with 130 nm technology. In the proposed dynamic comparator, both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 5GHz at supply voltage of 1.8V

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