Volume 3 - Issue 3
An Optimized Design of Approximate Multiplier by Partial Product Preforation
Abstract
Approximate computing appear as a promising solution to reduce their power dissipation. Such applications process large redundant data sets or noisy input data derived from the real world, do not have a golden result, perform statistical/probabilistic computations, and/or demand human interaction, thus their exactness is relaxed due to limited human perception. Approximate computing can be applied at both software and hardware levels. Hardware-level approximation mainly targets arithmetic units, such as adders and multipliers, widely used in portable devices to implement multimedia algorithms, e.g., image and video processing. Partial product generation, we introduce the partial product preforation method for creating approximate multipliers. Inspired from, we omit the generation of some partial products, thus reducing the number of partial products that have to be accumulated, we decrease the area, power, and depth of the accumulation tree.
Paper Details
PaperID: 6702759
Author Name: V.P. Sasikala and R. Dharmalingam
Author Email: -
Phone Number: -
Country: India
Keywords: Approximate Arithmetic Circuits, Approximate Computing, Approximate Multiplier, Error Analysis, Low Power.
Volume: Volume 3
Issues: Issue 3
Issue Type: Issue
Year: 2016
Month: September
Pages:150-156