Abstract

A digital system is tested and diagnosed during its lifetime on numerous occasions. For the system to perform its intended mission with high availability, testing and diagnosis must be quick and should have very high fault coverage. Universal Asynchronous Receiver Transmitter (UART) used for short distance, low speed, low cost data exchange between the processor and peripherals. There is a need for realizing the UART function in a single or few chips. Also, there is a need to ensure the data transfer is error proof. This paper targets the introduction of Built-in self test (BIST) with complete feedback shift register (CFSR) technique to UART, to overcome the testability and data integrity. The 8-bit UART with status register and BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.4 and realized on FPGA. The results indicate that this model eliminates the need for higher end, expensive testers and thereby it can reduce the development time and cost

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