Abstract

In this manuscript we introduce parallel-prefix architecture for the design ofmodulo2n+1 adder. The proposed architecture is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n+1addition.This sparse approach is enabled by the introduction of the inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed.

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