Abstract

In this paper of high performance input output blocks, the study and analyze high performance digitally controlled impedance IO standards design in terms of power consumption. The digitally controlled impedance calibration circuit has high accuracy in 7 series FPGA and supports all IO standards. The IO standards which support the controlled impedance drivers such as LVDCI_15, LVDCI_18, HSLVDCI_15, HSLVDCI_18, HSUL_12_ DCI, and DIFF_ HSUL_12_DCI are designed. The low power consumption methodologies for these IO standards are studied. Xilinx planhead and xPower analyzer is used to simulate, synthesize and implement low power design.

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