Abstract

This project presents the design of Adaptive Finite Impulse Response (FIR) filter based moving target detection in various clutter conditions in Radar Receiver. An adaptive system performs the processing by using an architecture having time-varying parameters on the received signals which accompanies with clutters. To reduce processing time as well as power, pipelined CORDIC architecture has been chosen for design of adaptive FIR filters in conjunction with very robust and popular LMS algorithm for filtering as well as weight update to suppress clutter of various intensity. The design of CORDIC in the circular rotation mode gives a high system throughput due to its pipelined architecture by reducing latency in each individual pipelined stage. Saving area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed design can be achieved through optimization in the number of micro rotations. The design has been synthesized and implemented on a Xilinx Virtex4 XC4VFX-12 FPGA device using 13.1 ISE design tool suite and results are shown and discussed. For better adaptation and performance of Adaptive Filters and to minimize quantization error, the numbers of iterations are also optimized.

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