Abstract

As multiple cell upsets (MCUs) become more frequent on SRAM storage devices, there is a growing interest on error correction codes that can correct multibit errors. MCUs affect cells that are close together, and hence the numbers of codes that can correct double-adjacent or triple-adjacent errors have been proposed. These codes, in many cases, do not require additional parity check bits and in the rest require only one or two additional bits. The decoding complexity improves but in many cases can still be invoked with limited impact on the memory speed. These codes are useful for applications in which the error rate is low, however, when the error rate is high, codes that can correct errors on multiple independent bits are needed. The proposed decoder is also able to correct triple-adjacent errors, thus covering the most common error patterns.

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